1. Field of the Invention
The present invention relates to a method for forming a multi-layer metal line of a semiconductor device, and in particular to an improved method for forming a multi-layer metal line of a semiconductor device wherein a insulating film having a low dielectric constant is used in a formation process of an interlayer insulating film of the multi-layer metal line to improve characteristics and reliability of the device.
2. Description of the Background Art
In general, a line of a semiconductor device for electrically connecting devices or device to an external circuit is formed by filling a contact hole and a via hole for interconnection with a line material to form a line layer, and performing subsequent processes. In particular, a metal line is used in a region where a low resistance is required.
The metal line is formed by filling the contact hole and the via hole with the line material, such as an aluminum alloy containing aluminum and a small amount of silicon and/or copper which has a low resistance and excellent processing characteristics according to sputtering of physical vapor deposition (PVD).
Due to a high integration tendency of the semiconductor device, in a process formation of a metal line, a low-K material layer having a low dielectric constant is formed as an interlayer insulating material to reduce resistance capacitance delay by spin coating, and a via hole for connecting an upper line to a lower line is formed, and filled the via hole to form a tungsten contact plug.
Here, since the insulating film is non-uniformly coated on the metal line by the spin-coating process, the thickness of the insulating film depends on a width and density of the metal line therebelow.
An inter-capacitance value between the upper metal line and the lower metal line varies due to non-uniform thickness according to the width and density of the metal line, which deteriorates characteristics of the device.
Moreover, bowing phenomenon occurs during a dry etching process of the via hole, which complicates etching conditions, and the bowing on the sidewalls of the via hole makes deposition of an adhesive film and a diffusion barrier film difficult, which complicates a subsequent process, namely a formation process of a tungsten contact plug.
Furthermore, the end of the metal line is shorted and rounded due to a proximate effect during the patterning process of the metal line, which reduces process margin in a via contact etching process. As a result, the characteristics of the device are deteriorated.
FIGS. 1a to 1e are cross-sectional views illustrating a conventional method for forming a multi-layer metal line of a semiconductor device.
Referring to FIG. 1a, a lower metal line 13 is formed on a semiconductor substrate 11. Here, the lower metal line 13 is composed of an aluminum alloy, and has Ti or Ti/TiN stacked layer at the upper and lower portions of the lower metal line 13.
Reference numeral 100 denotes a region where the area of the lower metal line varies, and reference numeral 200 denotes a region where the density of the lower metal line varies. That is, a metal line having a large area is formed at the left side of region 100, and a metal line having a small area is formed at the right side thereof. A density of the metal line at the left side of the region 200 is relatively higher than that of the right side thereof.
Thereafter, an insulating film 15 having a low dielectric constant is formed on the entire surface. Here, the insulating film 15 is formed according to spin coating using a material having a dielectric constant of about 3.
Although the insulating film 15 has an excellent filling property between metals, namely high step coverage, it is not uniformly coated on the metal line due to its adhesiveness, but unevenly coated on the metal line depending on a width and density of the metal line.
In general, the insulating film 15 is coated thicker on the metal line having the larger area than on the metal line having the smaller area, and in the region having high metal line density than the region having low metal line density.
Thereafter, an oxide film 17 is deposited on the insulating film 15 according to plasma enhanced chemical vapor deposition (PECVD).
Here, the oxide film 17 is formed using a material having a dielectric constant of about 4 at a thickness ranging from 5000 to 12000 xc3x85.
A chemical mechanical polishing (CMP) is performed on the oxide film 17 to form an interlayer insulating film having a stacked structure of the insulating film 15 and the oxide film 17.
As shown in FIG. 1b, a photosensitive film pattern 19 is formed on the interlayer insulating films 15 and 17.
Here, the photosensitive film pattern 19 is formed according to exposure and development processes using a via contact mask (not shown).
As illustrated in FIG. 1c, a via contact hole 21 exposing the lower metal line 13 is formed by etching the interlayer insulating films 17 and 15 using the photosensitive film pattern 19 as a mask.
Since an etch selectivityivity ratio of the insulating film 15 is at least 1.5 times higher than the etching selectivity ratio of the oxide film 17, a portion of the insulating film 15 which is thicker is laterally etched, thereby generating bowing.
In addition, a portion of the insulating film 15 at the side portions of the lower metal line 13 is etched due to a small process margin of the via contact etching process, and thus metallic polymers remain therein.
Referring to FIG. 1d, the residual photosensitive film pattern 19 is removed after the etching process, and a Ti/TiN film 23 which is an adhesive layer/diffusion barrier film is formed on the entire surface of the resulting structure including a sidewall and bottom of the via contact hole 21. Here, the Ti/TiN film 23 is thinly formed or rarely formed in a portion where bowing phenomenon occurs or metallic polymers remain.
As depicted in FIG. 1e, a tungsten layer 25 filling the via contact hole 21 is formed on the entire surface of the resulting structure.
The tungsten layer 25 is not deposited on a portion where the Ti/TiN film 23 is not deposited, thereby deteriorating the property of the device.
As described above, in the conventional method for forming the multi-layer metal line of the semiconductor device, a bowing phenomenon occurs in the subsequent process because the insulating film having the high etch selectivityivity ratio is laterally etched during the via contact etching process. Over-etching of the insulating film in the subsequent via contact process generates the metallic polymers because the process margin is reduced due to shorting or rounding in the metal line patterning process, thereby deteriorating the property and reliability of the device.
Accordingly, it is an object of the present invention to provide a method for forming a multi-layer metal line of a semiconductor device wherein high integration of the semiconductor device is achieved by forming a via contact plug without generating bowing or metallic polymers due to over-etching.
In order to achieve the above-described object of the invention, there is provided a method for forming a multi-layer metal line of a semiconductor device, including the steps of: forming a first insulating film having a low dielectric constant on a semiconductor substrate having a lower metal line thereon; planarizing the first insulating film until a predetermined thickness of the first insulating film remains on the lower metal line; removing the first insulating film on the lower metal line by plasma etching to expose a entire portion of the lower metal line; forming an etch barrier layer on the entire surface; forming a second insulating film having a low dielectric constant on the etch barrier layer; forming an oxide film on the second insulating film; etching the oxide film, the second insulating film and the etch barrier layer according to a photoetching process using a via contact mask to form a via contact hole exposing the lower metal line; forming an adhesive film/diffusion barrier film on the entire surface of the resulting structure including a sidewall of the via contact hole and the exposed portion of the lower metal line; and forming a contact plug filling the via contact hole, and forming an upper metal line contacting the contact plug.
On the other hand, the principle of the present invention will now be explained.
A first insulating film having a low dielectric constant (dielectric constant≈xcx9c3) is coated on a lower metal line, and then planarized to expose the lower metal line. An etch barrier layer (dielectric constant≈xcx9c4.5) is formed thereon, a planarized second insulating film having a low dielectric constant (dielectric constant≈xcx9c3) is formed thereon, and an oxide film (dielectric constant≈xcx9c4) is formed thereon, thereby forming an interlayer insulating film having a stacked structure of the first insulating film, the etch barrier layer, the second insulating film and the oxide film. Here, the first and second insulating films having low dielectric constants are formed thicker in the interlayer insulating film, and the etch barrier layer is formed with SiC having a low dielectric constant, thereby offsetting or decreasing an inter-capacitance.
In addition, each layer in the interlayer insulating film is etched under different conditions during a via contact etching process, thereby preventing generation of metallic polymers due to over-etching resulting from misalignment. Therefore, the property of the device is not degraded.